Search - vhdl serial

[VHDL-FPGA-Verilog] 用VHDL语言在CPLD上实现串行通信

Description: 用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication
Platform: | Size: 4096 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] 标准的串口通讯设计VHDL

Description: 标准的异步串口通讯设计程序——基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme
Platform: | Size: 10240 | Author: 于飞 | Hits:

[Documents] UART(FPGA)

Description: 基于FPGA的串行通信UART控制器，采用VHDL语言编写，包含多个子模块。在ISE或FPGA的其它开发环境下新建一个工程，然后将文档中的各个模块程序添加进去，即可运行仿真。源程序已经过本人的仿真验证。-FPGA-based UART serial communication controller, using VHDL language, includes a number of sub-module. ISE FPGA or in the other developing a new environment, then documentation of the various modules of procedures added to it, will be running simulation. I have been the source of the simulation.
Platform: | Size: 14336 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilog] chengxu(vhdl)

Description: 这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序-VHDL and FPGA prepared by the computer serial communication procedures and an LED procedures
Platform: | Size: 548864 | Author: 黄鹏飞 | Hits:

[VHDL-FPGA-Verilog] uart-verilog-vhdl

Description: 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
Platform: | Size: 294912 | Author: 刘索山 | Hits:

[VHDL-FPGA-Verilog] uart(serial)-200792511240998

Description: 基于vhdl 的串行接口具有完整的程序-VHDL-based serial interface with a complete process
Platform: | Size: 265216 | Author: weixing | Hits:

[Embeded-SCM Develop] high-speed-serialIO

Description: 高速串行IO方面的一本电子书，是xilinx公司发布的，认为相当不错，供大家一起学习-High-speed serial IO aspects of an e-book is issued by Xilinx Inc., consider pretty good for everyone to learn
Platform: | Size: 1708032 | Author: cao | Hits:

[VHDL-FPGA-Verilog] uart

Description: 串口通讯协议，你您可以自己建个工程，再将需要的VHDL文本，添加到工程中，理解程序在仿真！-Serial communication protocol, you can build your project, and then need VHDL text, added to the project, understand the procedures in the simulation!
Platform: | Size: 10240 | Author: 张亚伟 | Hits:

[VHDL-FPGA-Verilog] serial

Description: 串行口数据传输实验，vhdl源代码，完成信号发生，串并转换，检测电路-Serial port data transmission experiment, vhdl source code, complete the signal occurred, SERDES, detection circuit
Platform: | Size: 1024 | Author: yew | Hits:

[VHDL-FPGA-Verilog] uart_exam

Description: VHDL写的串口，很好用，程序非常简单，可以调试用-Written in VHDL serial, very good, and the procedure is very simple, you can debug with
Platform: | Size: 1024 | Author: jimmy | Hits:

[VHDL-FPGA-Verilog] UartControler3

Description: 串口程序 VHDL-Serial procedures VHDL
Platform: | Size: 646144 | Author: 吴多 | Hits:

[VHDL-FPGA-Verilog] uart_v11

Description: uart串口的vhdl语言程序。本人调试过，非常好用-serial UART VHDL Language Program. I debug, and very easy to use
Platform: | Size: 43008 | Author: hjj | Hits:

[VHDL-FPGA-Verilog] RS232

Description: 本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）；并在数据接收区显示接收到的字符。串口调试终端的设置：波特率115200，一个停止位，无校验位。-Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Platform: | Size: 730112 | Author: 李华 | Hits:

[VHDL-FPGA-Verilog] RS232uart(VHDL)

Description: 256字节深度的RS232串口程序,共分4个模块,顶层文件\FIFO程序\串口收和串口发.经过测试已用于产品.可靠!-Depth of 256-byte Serial RS232 procedures, divided into four modules, top-level document procedures FIFO serial and serial-fat collection. After the test has been used in products. Reliable!
Platform: | Size: 5120 | Author: 温海龙 | Hits:

[VHDL-FPGA-Verilog] VHDL-SPI-Module.doc

Description: 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmitted over the median, given by an external controller to control transmission pulse.
Platform: | Size: 37888 | Author: | Hits:

[VHDL-FPGA-Verilog] serial

Description: 基于VHDL的串口通信基于VHDL的串口通信-VHDL-based serial communication based on VHDL Serial Communication
Platform: | Size: 377856 | Author: 戴明 | Hits:

[Embeded-SCM Develop] serial

Description: -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在 --PC机上安装一个串口调试工具来验证程序的功能。 -- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控 --制器，10个bit是1位起始位，8个数据位，1个结束 --位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实 --现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是 --9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间 --划分为8个时隙以使通信同步. --程序的工作过程是：串口处于全双工工作状态，按动SW0，CPLD向PC发送“welcome" --字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向CPLD发送0-F的十六进制 --数据，CPLD接受后显示在7段数码管上。-- The module s function is to verify the implementation and the basic PC-to serial communication functions. Required at - PC machine on the installation of a serial debugging tools to verify the function of the procedure. - Implementation of a program to send and receive a 10 bit (that is, no parity bit) Serial Control - System, and 10 bit is a start bit, 8 data bits, 1 Ending - Bit. Serial Porter law procedures defined by the parameters div_par decision to change the parameters can be real - Is the corresponding baud rate. Procedures set div_par the current value is 0x104, the corresponding baud rate are - 9600. 8 times the baud rate with a clock will be sent or received every bit of the cycle time - Is divided into eight time slots in order to enable synchronous communication. - Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome" - String (serial debug tools is set to accept by way of A
Platform: | Size: 65536 | Author: johnson | Hits:

[Driver Develop] SIPO

Description: Filo Serial-Input to Paralle-output
Platform: | Size: 1024 | Author: Zorro | Hits:

[VHDL-FPGA-Verilog] vhdl-serial

Description: VHDL串口通信,实现数据的发送与接收，适合FPGA和CPLD芯片的开发-VHDL serial communication
Platform: | Size: 146432 | Author: 窦士 | Hits:

[Other] VHDL-serial-communication-program

Description: VHDL串口通信程序设计本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。-VHDL serial communication program design Function of this module is to verify the implementation and the basic functions of a PC serial communications. We need to install a serial debugging tools on the PC to verify the functionality of the program.
Platform: | Size: 7168 | Author: 曾 | Hits:

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[VHDL-FPGA-Verilog] 用VHDL语言在CPLD上实现串行通信

[VHDL-FPGA-Verilog] 标准的串口通讯设计VHDL

[Documents] UART(FPGA)

[VHDL-FPGA-Verilog] chengxu(vhdl)

[VHDL-FPGA-Verilog] uart-verilog-vhdl

[VHDL-FPGA-Verilog] uart(serial)-200792511240998

[Embeded-SCM Develop] high-speed-serialIO

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] serial

[VHDL-FPGA-Verilog] uart_exam

[VHDL-FPGA-Verilog] UartControler3

[VHDL-FPGA-Verilog] uart_v11

[VHDL-FPGA-Verilog] RS232

[VHDL-FPGA-Verilog] RS232uart(VHDL)

[VHDL-FPGA-Verilog] VHDL-SPI-Module.doc

[VHDL-FPGA-Verilog] serial

[Embeded-SCM Develop] serial

[Driver Develop] SIPO

[VHDL-FPGA-Verilog] vhdl-serial

[Other] VHDL-serial-communication-program

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